/*
 * File   : mac_top.v
 * Date   : 20171106
 * Author : Bibo Yang, rspwfpgas@163.com
 *
 */

`timescale 1ns/1ns
module mac_top(
    input  wire       RxClk,
    input  wire       RxDv,
    input  wire [3:0] RxData,
    output wire       TxClk,
    output wire       TxEn,
    output wire [3:0] TxData
);

// RGMII loopback
assign {TxClk, TxEn, TxData} = {RxClk, RxDv, RxData};

endmodule
